1. Field of the Invention
The present invention relates to a synchronizing circuit that synchronizes asynchronous signals and a digital signal processor (DSP) using same.
2. Description of the Related Art
FIG. 5 shows part of a prior art DSP 10 that processes digital audio signals with the time axis compressed. FIGS. 6A and 6B are timing charts showing operations of the configuration of FIG. 5.
As shown in (E) and (F) of FIG. 6A, an LR identification signal LRi and a digital serial audio signal DATi are synchronized in units of words. When the LR identification signal LRi is a high or a low, it indicates that the serial audio signal DATi is a left (L) or a right (R) audio signal, respectively. A D flip-flop 11 synchronizes the external asynchronous LR identification signal LRi to an internal clock .phi.o which is from a clock generating circuit 12, and outputs it as an LR identification signal LRo. The internal clock .phi.o has the same frequency as that of the external clock .phi.i. On the other hand, the digital serial audio signal DATi provided externally is held in D flip-flop 13 in synchronization with the external clock .phi.i. A signal processing circuit 14 processes the audio signal from the D flip-flop 13 in synchronization with the internal clock .phi.o and outputs a serial audio signal DATo. To secure a processing time in the signal processing circuit 14, the serial audio signal DATo delays from the serial audio signal DATi for about one cycle time of the LR identification signal. In (B) and (E) of FIG. 6A, data Lo1 and Ro1 of the serial audio signal DATo are obtained by processing data Li1 and Ri1 of the serial audio signal DATi with the signal processing circuit 14, respectively. As the LR identification signal LRi is an asynchronous signal for DSP 10 which processes in synchronization with the internal clock .phi.o, the relationship between rise times of the LR identification signal LRi and internal clock .phi.o is undefined and it differs from one audio device to another.
FIG. 6B corresponds to part of FIG. 6A and, as shown in (A) and (B) of FIG. 6B, when the LR identification signal LRi transits from a low to a high at the time t1 of the internal clock .phi.o, because of the slight change of the rise time of the LR identification signal LRi to the minus or the plus direction of the time axis, the LR identification signal LRo starts rising at the rising time t1 or the next rising time t2 as shown in (C) or (D) of FIG. 6B, generating a jitter corresponding to one clock cycle.
Therefore, as shown in (D) and (E) of FIG. 6A, while the LR identification signal LRo is a high, if the one-word data Lol of the serial audio signal DATo is fetched and converted to parallel data with synchronizing to the internal clock .phi.o, the most significant bit bn of the data Lo1 will be missing. For example, if the most significant bit bn is a minus sign bit and the next bit is zero, the data Lol will be mistaken as a plus value because of the missing bit and the quality of playback sound changes considerably.